1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having floating-gate storage elements and a driving method therefor.
2. Description of the Prior Art
FIG. 25 is a circuit block diagram showing a memory cell array of a conventional nonvolatile semiconductor memory device such as a NOR flash memory.
Referring to FIG. 25, the so-called floating-gate memory cell transistors are arranged on the intersections between word lines WLnxe2x88x921 to WLn+1 and bit lines BLnxe2x88x921 to BLn+1. The word lines are connected with the gates of the memory cell transistors and the bit lines are connected with the drains of the memory cell transistors.
The sources of the memory cell transistors belonging to the same memory cell columns are connected to source lines SL in common.
An overerased state of the flash memory is now described.
If any cell present on a bit line has a depressed threshold voltage Vth (Vth less than 0), the threshold voltages Vth of all the remaining cells present on the bit line cannot be correctly measured in a flash memory having the aforementioned NOR array structure or an array structure referred to as a DINOR (divided bit line NOR) structure described later. In other words, it is difficult to perform a normal read operation as to the memory cells connected to this bit line.
When the threshold voltage Vth of the memory cell arranged on the intersection between the bit line BLn and the word line WLn is depressed in FIG. 25, for example, the threshold voltages Vth of the remaining cells present on the bit line BLn cannot be measured due to influence by the cell located on the intersection between the bit line BLn and the word line WLn even if the threshold voltages Vth of the remaining cells are enhanced (Vth greater than 0). In other words, it follows that all threshold voltages Vth are measured as apparently not more than 0 V.
FIG. 26 illustrates apparent threshold voltage distribution of memory cell transistors including such an overerased memory cell. FIG. 26 shows distribution of the number (bit number) of memory cells having thresholds Vth.
When investigating the distribution of the thresholds Vth in the memory cell array including the overerased memory cell (having the depressed threshold voltage Vth) as described above, cells proportionate to the number of cells present on the same bit line are determined as having threshold voltages Vth less than zero.
Therefore, the number of bits apparently corresponding to the threshold voltages Vth of zero corresponds to the sum of the memory cells coupled to the bit line including such an overerased memory cell, as shown in FIG. 26.
Such a depressed cell can occur since electrons are accidentally excessively extracted from a floating gate in the flash memory.
Some conventional methods of selectively returning the threshold of an overerased memory cell to an enhanced state are now described as methods of repairing the overerased memory cell after an erase operation.
In the following description, the operation of returning the threshold voltage Vth of the overerased cell to the enhanced state is referred to as xe2x80x9cwrite-backxe2x80x9d.
Some methods have been reported in relation to write-back processing.
A method employing channel hot electrons (hereinafter abbreviated as CHE) is known as one of methods of injecting electrons into the floating gate of the cell in the flash memory.
Writing with CHE is a method of injecting high-energy electrons accelerated beyond the barrier height of an oxide film into a floating gate FG among channel electrons accelerated by a steep electric field in the vicinity of the drain of the memory cell.
FIG. 27 is a schematic sectional view of a flash memory cell for illustrating write-back of an overerased bit with CHE.
Referring to FIG. 27, a gate oxide film 13, a floating gate 14 consisting of polycrystalline silicon or the like, an insulating film 15 having a three-layer structure, referred to as an ONO structure, of an oxide film, a nitride film and an oxide film for preventing leakage and a control gate 16 consisting of polycrystalline silicon or the like are stacked on a P-type semiconductor substrate 11. N-channel source and drain regions 12a and 12b are formed in a self-alignment manner in proximity to the aforementioned stacked gates on the P-type semiconductor substrate 11.
A source voltage Vs, a drain voltage Vd, a control voltage Vcg and a substrate voltage Vsub are applied to the source region, the drain region, the control gate and the substrate 11 respectively. The control voltage Vcg is generally set higher than the drain voltage Vd.
The threshold voltage Vth of the memory cell can be enhanced by writing back the overerased cell in the CHE mode. However, the write-back in the CHE mode has the following problems:
First, the overerased cell must be selected. In other words, the write-back operation is performed after selecting the overerased cell, and hence the circuit structure for implementing selection of the overerased cell is disadvantageously complicated.
Second, a desired voltage for implementing the write-back operation in the CHE mode must be set between the drain and the gate. The desired voltage requires potential arrangement different from that bringing cell into a written state in general. The different potential arrangement is required since the width fluctuating the threshold voltage Vth of the memory cell to be written back is different from the fluctuation width in the conventional write operation.
Third, a channel current must be driven in write-back.
In order to drive the channel current, several 10 xcexcA is required for each cell as the drain current Id of the memory cell transistor.
The write-back operation in the CHE mode requires a circuit structure capable of selecting the overerased cell as described above.
A write-back method employing a gate current caused by drain avalanche hot electrons (hereinafter abbreviated as DAHE) or drain avalanche hot holes (hereinafter abbreviated as DAHH) is reported in xe2x80x9cA Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injectionxe2x80x9d by Yamada et al., IEEE Trans. Electron Devices, Vol. 43, p. 1937 (1996: hereinafter referred to as literature 1) as a method requiring no such bit selection.
A flash memory employing the CHE mode has a high P+ substrate concentration (up to about 1018 cmxe2x88x923) and a dense N+ diffusion layer (up to about 1020 cmxe2x88x923), in order to improve the efficiency of CHE. Spreading of a depletion layer is suppressed only in the P-type substrate region, for improving the CHE efficiency.
The aforementioned literature 1 also describes that the injection rate of As into the drain is 5xc3x971015 cmxe2x88x922, and the concentration of the N+ diffusion layer exceeds 1020 cmxe2x88x923 after heat treatment under such injection condition.
FIG. 28 is a conceptual diagram showing dependency of logarithmic values of the drain current Id and the gate current Ig on a gate voltage Vg in the flash memory cell having such a drain structure.
As to the gate current Ig, is known that currents of DAHH, DAHE and CHE modes are observed in a gate voltage region where the channel current flows from the lower side of the gate voltage Vg as shown in FIG. 28.
Such a state is described in the aforementioned literature 1 and other literature such as literature 2: xe2x80x9cA Novel Floating-Gate Method for Measurement of Ultra-Low Hole and Election Gate Currents in MOS Transistorsxe2x80x9d by Y. Nissan-Cohen, J. Electron Device Letter, Vol. EDL. 7, No. 10, Octeber, pp. 561-563 (1986) or U.S. Pat. No. 5,546,340 or literature 3: xe2x80x9cFailure Mechanisms of Flash Cell in Program/Erase Cyclingxe2x80x9d by P. Cappelletti et al., IEDM 94, pp. 291-294, for example.
As described below, an overerased state can be self-convergently written back by utilizing the DAHH/DAHE current mode.
FIG. 29 is a schematic sectional view for illustrating a conventional operation of writing back an overerased bit with DAHE/DAHH. Referring to FIG. 29, the memory cell is similar in structure to the aforementioned memory cell written back with CHE, and hence redundant description is not repeated.
However, the method of applying a voltage to an electrode is different. A GND level is applied with respect to Vcg and GND or negative bias is applied with respect to Vsub.
FIG. 30 shows a result of evaluation of write-back in the overerased bit write-back method with DAHE/DAHH as time change of the threshold voltage in a single cell. The cell structure, described with reference to FIG. 29, is equivalent to that shown in literature 1.
When left under conditions of a drain voltage Vd of 5 V and a control gate voltage Vcg of 0 V (Vs=Vsub=GND), the cell (white circles in FIG. 30) overerased to the threshold voltage Vth of about 0 V is written back to a convergence threshold voltage Vthc of up to 1.75 V after about 0.1 sec. Current sensitivity of a sense amplifier is set to 30 xcexcA.
This write-back method requires no bit selection dissimilarly to the method in the CHE mode but the cell may be left while applying the drain voltage to bit lines of the overall array while setting a gate potential (word line potential) to 0 V.
Further, the feature of this method resides in that, also in a memory cell (shown by white triangles (erect) in FIG. 30) whose threshold voltage Vth is higher than the convergence threshold voltage Vthc, the threshold voltage Vth fluctuates to the convergence threshold voltage Vthc.
In a cell whose threshold voltage Vth is lower than the convergence threshold voltage Vthc, injection (electron injection) of DAHE shown in FIG. 28 takes place to reduce the floating gate potential to a level Vg* in FIG. 28. Consequently, the threshold voltage Vth of the cell is written back to the convergence threshold voltage Vthc.
In the cell whose threshold voltage Vth is higher than the convergence threshold voltage Vthc, injection (hole injection) of DAHH shown in FIG. 28 takes place to increase the floating gate potential to the level Vg* in FIG. 28. Consequently, it follows that the threshold voltage Vth of the cell is reduced to the convergence threshold voltage Vthc.
That is, electron injection with DAHE and hole injection with DAHH are balanced at the convergence threshold voltage Vthc. In other words, both of electrons and holes are continuously injected into the floating gate of the memory cell whose control gate potential reaches Vg* in a balanced manner.
FIG. 31 shows drain voltage dependency in the overerased bit write-back method with DAHE/DAHH. The time required for write-back is increased as the drain voltage Vd is reduced from 6 V to 4 V.
FIG. 32 shows gate voltage-to-drain current characteristics (Vgxe2x88x92Id characteristics) in the cell reaching the convergence threshold voltage Vthc in the overerased bit write-back method with DAHE/DAHH.
Referring to FIG. 32, it is understood that a current flows in the written-back cell also when the gate potential Vg is 0 V. This measurement is made under the drain voltage Vd of 1 V, and a current of several xcexcA/bit flows in actual write-back with application of the drain voltage Vd of 5 V. This also applies to write-back conditions of 1 sec. with Vd of 4 V and 1 sec. with Vd of 6 V.
When the overall array is selected in place of bit line selection in the overerased bit write-back method with DAHE/DAHH, it follows that a current of about 500 mA flows per block even if the array block size is 256 bits (per bit line)xc3x972048 bits (per word line)=512 Kbits and a cell current at the convergence threshold voltage Vthc is 1 xcexcA/bit.
In other words, the driving current is disadvantageously increased in the write-back operation in this method.
Referring to the aforementioned literature 3, it is also reported that channel conductance is deteriorated in write-back with the DAHE/DAHH gate current.
This is because both of electrons and holes are continuously injected into the floating gate through the oxide film at the convergence threshold voltage Vthc, to result in deterioration of the gate oxide film.
The inventors have proposed a write-back method with subthreshold CHE as a method of self-selectively writing back an overerased cell on a selected bit line while setting a word line in a non-selected state.
FIG. 33 is a conceptual diagram showing the structure of a section of a drain part of a memory cell transistor subjected to such write-back.
As described later in detail, a floating gate 4 is provided on a P+ region of the main surface of a P-type substrate through a gate oxide film. An N++ drain region 2b for field relaxation is provided between an N+ drain region 2bb and the floating gate 4, dissimilarly to the structure shown in FIG. 27.
When further increasing CHE write efficiency through the structure shown in FIG. 33, CHE writing at a lower drain voltage is enabled.
It has been found that, in this case, a channel current is energetically accelerated in a high field region close to a drain at a drain voltage lower than that in the conventional write-back with DAHE/DAHH, the channel current flowing in a threshold region is consequently energetically accelerated in the high field region close to the drain as compared with a gate current Ig component generated by injection of part of secondarily generated DAHE/DAHH into a gate oxide film and a gate current generated by CHE components resulting from injection of part of the channel current into the gate oxide film becomes larger.
FIG. 34 shows dependency of the gate current Ig on the gate voltage Vg under such operating conditions enabling write-back with subthreshold CHE.
FIG. 34 also shows the characteristics shown in FIG. 28 for the purpose of comparison.
The difference between this method and the conventional self-selective write-back with DAHE/DAHH shown in FIG. 28 resides in that only electrons are injected in the write-back with subthreshold CHE.
This is clearly understood by observing the Vgxe2x88x92Id characteristics after convergence.
In the self-selective write-back with DAHE/DAHH, the threshold voltage Vth converges to the level where electrons and holes are balanced. As shown in FIG. 32, therefore, the channel current flows in the Vgxe2x88x92Id characteristics of the memory cell after convergence also when the control gate potential Vcg is 0 V. In other words, the memory cell transistor is not cut off also when Vcg=0 V.
FIG. 35 shows gate voltage-to-drain current characteristics (Vgxe2x88x92Id characteristics) of a cell reaching the convergence threshold voltage Vthc in the overerased bit write-back method with subthreshold CHE.
Referring to FIG. 35, white circles show initial characteristics, white triangles (erect) show characteristics after performing write-back with subthreshold CHE for 1 msec. under conditions of the drain voltage of 4 V and Vcg=0 V, and inverted triangles show characteristics after performing write-back with subthreshold CHE for 1 sec. respectively.
In the overerased bit write-back with subthreshold CHE, a channel current slightly flowing when the control gate potential Vcg is 0 V is injected into a gate and hence the channel current is cut off in the Vgxe2x88x92Id characteristics of the memory cell after convergence.
In the self-selective write-back with subthreshold CHE, therefore, the threshold voltage Vth does not fluctuate in a cell whose threshold Vth is higher than the convergence threshold voltage Vthc, i.e., in which the channel current is cut off, while the threshold voltage Vth is increased only in a cell whose threshold voltage Vth is lower than the convergence threshold voltage Vthc, i.e., in which the channel current is not cut off.
FIG. 36 shows initial threshold dependency of time fluctuation of thresholds of cells subjected to write-back with subthreshold CHE.
It is understood that the threshold voltage Vth is increased only in the cell in which the channel current is not cut off as described above.
FIG. 37 is a diagram for illustrating convergence times of thresholds in the case of performing write-back with subthreshold CHE.
As to memory cell transistors having initial thresholds of 0 V and 1 V, it is understood that the thresholds approximate to a convergence value after a lapse of about 10 msec. under conditions of the drain voltage Vd of 4 V and Vcg=0 V.
FIG. 38 is a diagram for illustrating applied drain voltage dependency of convergence of thresholds in the write-back with subthreshold CHE.
FIG. 39 is a diagram for illustrating applied drain voltage dependency of convergence of thresholds in the case of performing write-back with subthreshold CHE in a drain voltage region lower than that shown in FIG. 38.
FIG. 40 illustrates distribution of threshold voltages after performing write-back with subthreshold CHE on a 256 K-bit array.
Referring to FIG. 40, white circles show characteristics after an erase operation, and white triangles (erect) show characteristics after a lapse of 50 msec. under conditions of the drain voltage Vd of 4.5 V and the control gate voltage Vcg of 0 V.
In such a self-selective write-back method with subthreshold CHE, only electrons are injected to cause no deterioration of channel conductance dissimilarly to the write-back with DAHE/DAHH.
The characteristics of the aforementioned write-back methods are summarized as follows:
I) Write-back method in CHE Mode
In this case, a potential different from that in a write operation for a cell is disadvantageously required, with requirement for bit selection of an overerased cell.
Further, a driving current in write-back is problematically large. This results from the mode of injecting CHE generated by positively feeding a channel current into a floating gate.
II) Self-Selective Write-back with DAHE/DAHH Gate Current
In this case, no bit selection is required but write-back can advantageously be made in a self-selective manner. Further, the generated potential may be set substantially identically to that in writing.
When voltage reduction takes place, however, the time required for convergence is disadvantageously increased. For example, a time of about 0.1 sec. to 1 sec. may be required. Further,
Further a driving current in write-back must disadvantageously be large. This results from a convergence current flowing in the overall array. In addition, channel conductance of the cell is deteriorated due to simultaneous injection of electrons and holes.
III) Self-Selective Write-back with Subthreshold CHE Gate Current
No bit selection is required but write-back can advantageously be made in a self-convergent manner. Further, the generated potential may be set substantially identically to that in writing.
When voltage reduction takes place, however, the time required for convergence is disadvantageously increased, similarly to the self-selective write-back with the DAHE/DAHH gate current.
In this case, the time required for write-back is typically about 100 msec.
There is such a tendency that the channel current is cut off as the write-back progresses and hence the driving current is reduced, while only electrons are injected and hence the channel conductance is not deteriorated.
Comparing the aforementioned three methods with each other, at least the self-convergent (self-selective) write-back method is advantageous for cost reduction since the circuit scale required for bit specification of an overerased cell is reduced.
However, the self-selective write-back in the subthreshold CHE mode or the DAHE/DAHH mode also has the following problem:
In recent years, requirement for a flash memory having a single power source is increased and a potential to bit lines must be driven with a charge pump circuit CP.
In this case, no write-back is performed in the self-selective write-back method unless sufficient attention is paid to off-state leakage of the memory cells.
FIG. 41 is a flow chart for illustrating an erase sequence in self-selective write-back.
When the erase sequence of the conventional self-selective write-back is started (step S100), a pre-erase write operation (step S104) is performed and thereafter application of an erase pulse (step S106) and an erase verify operation (step S108) are repeated until the threshold voltage Vth of a bit having the highest threshold is reduced below an erase verify level in post-erase threshold voltage Vth distribution.
After completion of the erase operation, a write-back pulse is added for self-selectively writing back an overerased bit present on a bit line supplied with a bit line potential (step S110).
In this method, however, write-back may not function unless design is made with sufficient attention paid to sense current sensitivity and the size of the array subjected to collective write-back.
FIG. 42 illustrates gate potential-to-drain current characteristics (Vgxe2x88x92Id characteristics) of an erased unit cell.
In the circuit of the flash memory, the threshold voltage Vth is defined in the value of the gate potential Vg when a cell current value reaches a certain standard value.
Assuming that the cell current standard value is 30 xcexcm in a single end sense amplifier, the post-erase threshold voltage Vth of the cell shown in FIG. 42 is 2.4 V.
It is to be noted that an off-state leakage current (hereinafter denoted by Ioff) of up to about several nA flows in this cell also when the gate potential Vg is 0 V.
In the write-back operation (typically under operating conditions of the drain voltage Vd of 5 V and the gate potential Vg of 0 V) employing the self-selective write-back method, therefore, it follows that a small off-state leakage current flows even in a non-overerased cell having a threshold voltage Vth of 2.4 V.
In other words, unignorable off-state leakage Ioff is present depending on post-erase threshold voltage Vth distribution in the write-back operation also when performing self-convergent write-back with subthreshold CHE in the conventional erase method performing write-back after erase verification. In other words, it follows that such off-state leakage Ioff flows also when the word line potential is 0 V since not all cells are cut off.
It is important to take such an off-state leakage value into consideration in order to effectuate write-back. The problem of the off-state leakage current value is now described in more detail with reference to examples.
FIG. 43 illustrates distribution of post-erase threshold voltages Vth. Referring to FIG. 43, white circles show measured values, while black circles, black triangles (erect), black squares and black triangles (inverted) show Gaussian distribution with thresholds of 2.4 V, 2 V, 1.6 V and 1.2 V respectively. It is understood that the distribution of the threshold voltages Vth can be substantially approximated with Gaussian distribution except behavior of tail bits (bits on the bottoms of the distribution).
FIG. 44 shows calculated sums of off-state leakage in the erase threshold Vth distribution (distribution as to 1-Mbit memory cells). The off-state leakage values vary with the positions of the erase threshold Vth distribution.
Referring to FIG. 44, the sums of bit off-state leakage located on the respective thresholds Vth are shown on the vertical axis in the erase threshold Vth distribution. The off-state leakage values are increased as the erase threshold Vth distribution is shifted to the lower Vth side.
FIG. 45 shows the sum of off-state leakage in the overall post-erase threshold voltage Vth distribution of a 64-KB (512-Kbit) block in the case of defining the threshold voltage Vth with the sense current sensitivity of 30 xcexcA. Referring to FIG. 45, the total of the threshold voltages Vth in FIG. 44 is shown on the vertical axis.
When calculating the sum of the in-block off-state leakage in FIG. 45, the erase threshold Vth distribution is approximated to Gaussian distribution and the horizontal axis shows peak positions of the erase threshold Vth distribution.
In the case of a peak value Vth.peak (2.5 V) in the threshold distribution, the sum of the off-state leakage reaches 4 mA, which is too large for a general circuit structure as described below.
In general, an external single power source is required as the product standard of a flash memory, as described above. Therefore, the charge pump circuit CP is employed for driving the bit line current in the write operation. The upper limit of charge pump driving is about several mA in current value, depending on the mode and the area of the charge pump.
When the current value exceeds the upper limit, no desired voltage can be extracted from the charge pump but its output voltage is reduced. Also in the write-back operation, the charge pump circuit CP applies a voltage to the bit line.
In general, an erase verify value of the erase threshold Vth, i.e., the value of a bit having the highest threshold Vth in the erase threshold Vth distribution is set to about 3.5 V. Spreading of the erase threshold Vth distribution is up to about 1 V in half breadth (refer to FIG. 43), and hence the peak value Vth.peak of the erase threshold distribution can be about 2.5 V.
In other words, the sum of the off-state leakage of the erase threshold Vth distribution already reaches a value of about the upper limit of the driving current of the charge pump in a state performing general erasing, as shown in FIG. 45.
The voltage drivable by the charge pump is extremely reduced when exceeding the upper limit of the driving current. On the other hand, the write-back characteristics with subthreshold CHE are remarkably slowed when the bit line voltage is reduced, as shown in FIGS. 38 and 39.
When the sum of the off-state leakage of the erase threshold Vth distribution already reaches a value of about the upper limit of the driving current of the charge pump in the aforementioned state of performing general erasing, therefore, the voltage driven by the bit line may be reduced to result insufficient function of write-back, i.e., overerasing may be unrepairable.
Thus, it is problematic in a self-selective write-back operation that the bit line potential is reduced due to the sum of off-state leakage of the erase threshold Vth to result in ineffective write-back.
An object of the present invention is to provide a nonvolatile semiconductor memory device performing self-selective write-back after completion of erase verification, which can suppress reduction of a bit line potential in the write-back with an off-state leakage current.
Briefly stated, the present invention is directed to a nonvolatile semiconductor memory device formed on a semiconductor substrate, which comprises an internal power supply circuit, a control circuit, a memory cell array, a reference potential generation circuit, a cell potential supply circuit and a sense amplifier part.
The internal power supply circuit receives an external power supply potential and generates an internal power supply potential. The control circuit controls an operation of the nonvolatile semiconductor memory device in response to a command signal.
The memory cell array has a plurality of floating-gate memory cell transistors arranged in rows and columns. The memory cell array is divided into a plurality of memory cell blocks forming units subjected to an erase operation by repeating collective application of an erase pulse to the memory cell transistors and an erase verify operation respectively.
The reference potential generation circuit generates a reference potential for threshold determination of the memory cell transistors.
The cell potential supply circuit selects a memory cell transistor for selectively supplying the reference potential to the selected memory cell transistor in the erase verify operation and selectively supplying the internal power supply potential to the selected memory cell transistor in a write-back operation performed after completion of the erase verify operation respectively.
The sense amplifier part includes a plurality of sense amplifiers for reading data from the selected memory cell transistor and performing threshold determination on the basis of the value of a current flowing through the selected memory cell transistor in the write-back operation.
Current sensitivity of the sense amplifiers in the threshold determination is so set that the sum of leakage currents in off states of a plurality of memory cell transistors collectively subjected to the write-back operation is within the range of current drivability of the internal power supply circuit after completion of the erase verify operation.
According to another aspect of the present invention, a nonvolatile semiconductor memory device formed on a semiconductor substrate comprises an internal power supply circuit, a control circuit, a memory cell array, a reference potential generation circuit, a cell potential supply circuit and a sense amplifier part.
The internal power supply circuit receives an external power supply potential and generates an internal power supply potential. The control circuit controls an operation of the nonvolatile semiconductor memory device in response to a command signal.
The memory cell array has a plurality of floating-gate memory cell transistors arranged in rows and columns. The memory cell array is divided into a plurality of memory cell blocks forming units subjected to an erase operation by repeating collective erase pulse application to the memory cell transistors and an erase verify operation respectively.
The reference potential generation circuit generates a reference potential for threshold determination of the memory cell transistors.
The cell potential supply circuit selects a memory cell transistor for selectively supplying the reference potential to the selected memory cell transistor in the erase verify operation and selectively supplying the internal power supply potential to the selected memory cell transistor in a write-back operation performed after completion of the erase verify operation respectively.
The sense amplifier part includes a plurality of sense amplifiers for reading data from the selected memory cell transistor and performing threshold determination on the basis of the value of a current flowing through the selected memory cell transistor in the write-back operation.
The reference potential is so set that the sum of leakage currents in off states of a plurality of memory cell transistors collectively subjected to the write-back operation is within the range of current drivability of the internal power supply circuit after completion of the erase verify operation.
According to still another aspect of the present invention, a nonvolatile semiconductor memory device formed on a semiconductor substrate comprises an internal power supply circuit, a control circuit, a memory cell array, a reference potential generation circuit, a cell potential supply circuit and a sense amplifier part.
The internal power supply circuit receives an external power supply potential and generates an internal power supply potential. The control circuit controls an operation of the nonvolatile semiconductor memory device in response to a command signal.
The memory cell array has a plurality of floating-gate memory cell transistors arranged in rows and columns. The memory cell array is divided into a plurality of memory cell blocks forming units subjected to an erase operation by repeating collective erase pulse application to the memory cell transistors and an erase verify operation.
The reference potential generation circuit generates a reference potential for threshold determination of the memory cell transistors.
The cell potential supply circuit selects a memory cell transistor for selectively supplying the reference potential to the selected memory cell transistor in the erase verify operation and selectively supplying the internal power supply potential to the selected memory cell transistor in a write-back operation respectively.
The sense amplifier part includes a plurality of sense amplifiers for reading data from the selected memory cell transistor and performing threshold determination on the basis of the value of a current flowing through the selected memory cell transistor in the write-back operation.
The control circuit collectively performs the write-back operation in units of the memory cell transistors of a number smaller than the number of the memory cell transistors included in the memory cell blocks.
According to a further aspect of the present invention,-an erase method for a nonvolatile semiconductor memory device comprises steps of repeating a collective erase operation for a memory cell block including a plurality of memory cell transistors and an erase verify operation until the thresholds of the memory cell transistors fall below a prescribed verify level and bringing a word line into a non-selected state and collectively performing a self-selective write-back operation for a memory cell in an overerased state on a selected bit line with respect to subblocks each including memory cell transistors of a bit number less than the bit number of the memory cell block after completion of the erase verify operation.
According to a further aspect of the present invention, an erase method for a nonvolatile semiconductor memory device comprises steps of performing a collective erase operation for a memory cell block including a plurality of memory cell transistors, bringing a word line into a non-selected state and collectively performing a self-selective write-back operation for a memory cell in an overerased state on a selected bit line with respect to a plurality of memory cell transistors and repeating the erase operation and the write-back operation until the thresholds of the memory cell transistors fall below a prescribed verify level.
According to a further aspect of the present invention, an erase method for a nonvolatile semiconductor memory device comprises steps of repeating a collective erase operation on a memory cell block until the threshold of a memory cell transistor in the memory cell block falls below a first prescribed verify level, performing a collective erase operation on the memory cell block after the threshold of the memory cell transistor in the memory cell block falls below the first prescribed verify level, bringing a word line into a non-selected state and collectively performing a self-selective write-back operation for a memory cell in an overerased state on a selected bit line with respect to a plurality of memory cell transistors and repeating the erase operation and the write-back operation until the thresholds of the memory cell transistors fall below a second prescribed verify level lower than the first prescribed verify level.
According to a further aspect of the present invention, an erase method for a nonvolatile semiconductor memory device comprises steps of performing a collective erase operation on a memory cell block including a plurality of memory cell transistors, determining whether or not the sum of leakage currents in off states is in excess of a prescribed value as to a plurality of memory cell transistors, bringing a word line into a non-selected state and collectively performing a self-selective write-back operation for a memory cell in an overerased state on a selected bit line with respect to a plurality of memory cell transistors when the sum of the leakage currents is in excess of the prescribed value and repeating the erase operation, the determination and the write-back operation until the thresholds of the memory cell transistors fall below a prescribed verify level.
Thus, a principal advantage of the present invention resides in that a write-back operation can be reliably performed while suppressing increase of an off-state leakage current generated by setting post-erase threshold Vth distribution.
Another advantage of the present invention resides in that it is possible to reliably perform a write-back operation while suppressing increase of an off-state leakage current generated by setting post-erase threshold Vth distribution. Further, a potential is supplied to a bit line of a cell array while setting a word line in a non-selected state and an overerased cell present on the bit line supplied with the potential can be self-selectively reliably written back.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.